Semiconductor devices such as logic and memory devices are typically fabricated by a sequence of processing steps applied to a specimen. The various features and multiple structural levels of the semiconductor devices are formed by these processing steps. For example, lithography among others is one semiconductor fabrication process that involves generating a pattern on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated on a single semiconductor wafer and then separated into individual semiconductor devices.
Metrology processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers to promote higher yield. Optical metrology techniques offer the potential for high throughput without the risk of sample destruction. A number of optical metrology based techniques including scatterometry and reflectometry implementations and associated analysis algorithms are commonly used to characterize critical dimensions, film thicknesses, composition, overlay and other parameters of nanoscale structures.
Semiconductor devices are often fabricated by depositing a series of layers on a substrate. Some or all of the layers include various patterned structures. The relative position of structures both within particular layers and between layers is critical to the performance of completed electronic devices. Overlay refers to the relative position of overlying or interlaced structures on the same or different layers of a wafer. Overlay error refers to deviations from the nominal (i.e., desired) relative position of overlying or interlaced structures. The greater the overlay error, the more the structures are misaligned. If the overlay error is too great, the performance of the manufactured electronic device may be compromised.
Scatterometry overlay (SCOL) metrology techniques have been applied to the characterization of overlay errors. These methods are based primarily on differential measurements of optical signals corresponding to diffraction from two different targets each with programmed overlay offsets. The unknown overlay error is extracted based on these differential measurements.
In most existing methods, overlay error is characterized based on a metric sensitive to asymmetry of the structure. For example, existing angle-resolved scatterometry overlay (SCOL) involves a characterization of the asymmetry between the +1 and −1 diffracted orders that is indicative of overlay error. However, relying on asymmetry as the indicator of overlay error is problematic because other asymmetries such as line profile asymmetry or beam illumination asymmetry couple into the overlay-generated asymmetry in the measurement signal. This results in an inaccurate measurement of overlay error.
In existing methods, overlay error is typically evaluated based on measurements of specialized target structures formed at various locations on the wafer by a lithography tool. The target structures may take many forms, such as a box in box structure. In this form, a box is created on one layer of the wafer and a second, smaller box is created on another layer. The localized overlay error is measured by comparing the alignment between the centers of the two boxes. Such measurements are taken at locations on the wafer where target structures are available.
Unfortunately, these specialized target structures often do not conform to the design rules of the particular semiconductor manufacturing process being employed to generate the electronic device. This leads to errors in estimation of overlay errors associated with actual device structures that are manufactured in accordance with the applicable design rules. For example, image-based overlay metrology often requires the pattern to be resolved with an optical microscope that requires thick lines with critical dimensions far exceeding design rule critical dimensions. In another example, angle-resolved SCOL often requires large pitch targets to generate sufficient signal at the +1 and −1 propagating diffraction orders from the overlay targets. In some examples, pitch values in the range 500-800 nm may be used. Meanwhile, actual device pitches for logic or memory applications (design rule dimensions) may be much smaller, e.g., in the range 100-400 nm, or even below 100 nm.
Future overlay metrology applications present challenges for metrology due to increasingly small resolution requirements and the increasingly high value of wafer area. Thus, methods and systems for improved overlay measurements are desired.